Semiconductor devices use the conductive properties of semiconductor materials. Such semiconductor materials may include, for example, silicon (Si) or Si-containing materials, germanium (Ge), or materials including gallium nitride (GaN).
In particular, GaN semiconductor devices are increasingly desirable for power semiconductor devices because of their ability to carry large current and support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET). These types of devices can typically withstand high voltages while operating at high frequencies.
One example of a GaN HEMT device includes a semiconductor substrate (e.g., a Si substrate) with at least two interior layers. The different interior layers have different band gaps, which causes polarization that contributes to a conductive two-dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap. In a GaN semiconductor device, the layers that cause polarization typically include a barrier layer of AlGaN formed adjacent to a current conducting layer of GaN. The polarization creates the 2DEG region in the current conducting layer, allowing charge to flow through the device. This barrier layer may be doped or undoped.
Because a 2DEG region typically exists under the gate of a GaN transistor device when the gate is at zero gate bias, most GaN devices are normally on, or depletion mode devices. If the 2DEG region can be depleted, i.e. removed, when the gate is at zero applied gate bias, the GaN device can operate as an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
FIG. 1 illustrates a conventional GaN transistor device 100. Device 100 includes: a substrate 11, which may be composed of, for example, silicon (Si), silicon carbide (SiC), sapphire, or other material; one or more transition layers 12 formed over the substrate 11, which may be composed of layers of aluminum nitride (AlN) and aluminum gallium nitride (AlGaN) each about 0.1 to about 1.0 μm in thickness; a buffer layer 13 formed over the one or more transition layers 12, which is typically composed of GaN and typically about 0.5 to about 3 μm in thickness; a current conducting region 14 formed over the buffer layer 13 for providing a current conducting channel, which may be composed of GaN or indium gallium nitride (InGaN) typically about 0.01 to about 0.1 μm in thickness; contact regions 15 formed over or beside the current conducting region 14, which are typically composed of AlGaN, Al, titanium (Ti), and Si, and which may typically be about 0.01 to about 0.03 μm in thickness; a barrier layer 16 formed over the current conducting region 14 and between the contact regions 15, which is typically composed of AlGaN where the Al to Ga ratio is about 0.1 to about 1 with a thickness of about 0.01 to about 0.03 μm; a gate structure 17 formed over the barrier layer 16 and composed of p-type GaN with a nickel (Ni) and gold (Au) metal contact; and ohmic contact metals 18, 19 formed over the contact regions 15 at a source and drain contact areas, respectively, which may be composed of Ti and Al with a capping metal such as Ni and Au. Current conducting region 14, contact regions 15, and barrier layer 16 collectively form a device layer that provides for electrical connection to and control of device 100.
FIG. 2 illustrates another conventional GaN transistor device 200. Device 200 includes substrate 21, transition layers 22, buffer layers 24, channel layer 25, contact region 26, barrier layer 27, gate structure 28, and source and drain contact 29 and 30. These layers may have similar parameters as those described for FIG. 1. In addition, device 200 has a through-wafer via 20 that extends from a top side contact (i.e., from source contact 30, as shown in FIG. 2, or from drain contact 29) and through all material layers including the substrate to a metal layer 31 on the bottom side of the substrate 21. Metal layer 31 may be, for example, a heat sink.
FIG. 3 illustrates another GaN transistor device 300. Device 300 includes substrate 41, transition layers 42, buffer layers 43, current conducting region 44 including a channel layer, contact region 45, barrier layer 47, gate structure 48, and source and drain contacts 46 and 49. These layers may have similar parameters as those described for FIGS. 1 and 2. Device 300 includes a substrate connection via 40 that connects substrate 41 to the source contact 49. Unlike the via 20 of semiconductor device 200 (FIG. 2), via 40 of semiconductor device 300 terminates in substrate 41 without extending all the way to the backside of substrate 41.
Via connections such as those described in connection with FIGS. 2 and 3 provide a very low inductance and low resistance path from the back side of the semiconductor device (e.g., the backside of the substrate) to a front side connection of the device (e.g., a source or drain contact, gate structure, or other element). This is important for the high frequency operation for which these devices are intended. Conventional GaN transistor devices 100, 200, and 300 have disadvantages. Device 100 (FIG. 1) has a floating substrate potential when conducting substrates 11, such as Si, are used. This can lead to inadvertent device turn-on if the substrate voltage becomes too positive. In addition, negative substrate voltage can lead to resistance increase of the device 100. Devices 200 and 300 (FIGS. 2, 3) address this problem by electrically tying the respective substrates 21, 41 to the respective contacts 30, 49. For integrated devices, however, the desired substrate potential can be different for each device. Electrically connecting the substrate to the contact may result in some integrated devices having non-optimal substrate potentials.
In addition, it is often desirable to have a heat sink connected on the back side of a device, as shown, for example, with heat sink 31 of device 200 (FIG. 2). Electrically connecting the substrate 21 to the contact 30 may result in an undesirable voltage being present at the heat sink 31, unless intervening insulating material is included between the heat sink 31 and the substrate 21. Including insulating material between the heat sink 31 and the substrate 21, however, can be detrimental to the effectiveness of the heat sink 31. Insulating material adds thermal resistance, and the insulating material between 31 and 21 keeps heat inside the device. It often becomes necessary to include this material nonetheless, such as when multiple devices are used to form a circuit and utilize the same heat sink.
One example where it is undesirable, but often necessary, to include insulating material between the heat sink 31 and the substrate 21 is when two GaN field effect transistors (“FETs”) are connected in series to form a buck converter. A first FET in a buck converter has a source connected to ground, and a drain connected to a switch node. The second device has a source connected to the switch node and a drain connected to a high voltage. Thus, the two FET devices are connected to the same potential at the switch node, and are turned on in alternating fashion, such that the switch node voltage alternates between ground and high potential. If the entire substrate is connected to ground (i.e., the first FET device's source potential), then the second device's source will become high in potential relative to the substrate, leading to very large resistance increase in this second FET device. If the substrate potential is set to a switch node voltage, the first device will have high negative potential relative to the substrate beneath the source, and its resistance will become high.
It would therefore be desirable to be able to control the potential under each contact of an integrated semiconductor device independently, while also having the flexibility to set the back side of the semiconductor device at an independent potential.
The GaN family of materials, including AlGaN, InGaN, and InAlGaN, are all direct band gap materials. This leads to unique device behavior, such as light generation when electrons recombine with holes, very short minority carrier lifetimes, and rapid carrier generation during avalanche events. The latter characteristic makes GaN device very difficult to control when an avalanche event occurs, and generally leads to destruction of the part. Si, on the other hand, has an indirect band gap, allowing for smooth and controlled avalanche, and safe device operation under avalanche conditions.
It would therefore be desirable to combine the advantageous avalanche capabilities of the Si based devices with the improved speed and resistance characteristics of GaN in a single device.